This HTML version of the file intel.doc from the
PC Game Programmer's guide was produced by
Zack T Smith .
HTML modifications are therefore copyrighted ©
2005 by Zack T Smith, all rights reserved.
This information is provided in the hope that it will be useful,
but without any warranty; it is provided AS-IS,
without even the implied warranty of fitness for a particular purpose.
Intel 8086 Family Architecture
General Purpose Registers
AH/AL AX (EAX) Accumulator
BH/BL BX (EBX) Base
CH/CL CX (ECX) Counter
DH/DL DX (EDX) Data
(Exx) indicates 386+ 32 bit register
Segment Registers
CS Code Segment
SS Stack Segment
DS Data Segment
ES Extra Segment
(FS) 386 and newer
(GS) 386 and newer
Pointer Registers Stack Registers
SI (ESI) Source Index SP (ESP) Stack Pointer
DI (EDI) Destination Index BP (EBP) Base Pointer
IP Instruction Pointer
Status Registers
FLAGS Status Flags
Special Registers (386+ only)
CR0 Control Register 0 DR0 Debug Register 0
CR2 Control Register 2 DR1 Debug Register 1
CR3 Control Register 3 DR2 Debug Register 2
DR3 Debug Register 3
TR4 Test Register 4 DR6 Debug Register 6
TR5 Test Register 5 DR7 Debug Register 7
TR6 Test Register 6
TR7 Test Register 7
Default Segment Valid Overrides
BP SS DS, ES, CS
SI or DI DS ES, SS, CS
DI strings ES None
SI strings DS ES, SS, CS
Instruction Clock Cycle Calculation
Some instructions require additional clock cycles due to a "Next
Instruction Component" identified by a "+m" in the instruction
clock cycle listings. This is due to the prefetch queue being
purge on a control transfers. Below is the general rule for
calculating "m":
88/86 not applicable
286 "m" is the number of bytes in the next instruction
386 "m" is the number of components in the next instruction
(the instruction coding (each byte), plus the data and
the displacement are all considered components)
8088/8086 Effective Address (EA) Calculation
Description Clock Cycles
Displacement 6
Base or Index (BX,BP,SI,DI) 5
Displacement+(Base or Index) 9
Base+Index (BP+DI,BX+SI) 7
Base+Index (BP+SI,BX+DI) 8
Base+Index+Displacement (BP+DI,BX+SI) 11
Base+Index+Displacement (BP+SI+disp,BX+DI+disp) 12
add 4 cycles for word operands at odd addresses
add 2 cycles for segment override
80188/80186 timings differ from those of the 8088/8086/80286
Task State Calculation
"TS" is defined as switching from VM/486 or 80286 TSS to one of
the following:
New Task
Old Task 486 TSS (VM=0) 486 TSS (VM=1)
386 TSS (VM=0) 386 TSS (VM=1) 286 TSS
386 TSS (VM=0) 309 226 282
386 TSS (VM=1) 314 231 287
386 CPU/286 TSS 307 224 280
486 CPU/286 TSS 199 177 180
Miscellaneous
All timings are for best case and do not take into account wait
states, instruction alignment, the state of the prefetch queue,
DMA refresh cycles, cache hits/misses or exception processing.
To convert clocks to nanoseconds divide one microsecond by the
processor speed in MegaHertz:
(1000MHz/(n MHz)) = X nanoseconds
FLAGS - Intel 8086 Family Flags Register
Bit # (in hex) Acronym Description
0 CF Carry flag
1 1
2 PF Parity
3 0
4 AF Auxiliary flag
5 0
6 ZF Zero flag
7 SF Sign flag
8 TP Trap flag (single step)
9 IF Interrupt flag
A DF Direction flag
B OF Overflow flag
C,D IOPL IOPL I/O Privilege Level (286+ only)
E NT Nested Task Flag (286+ only)
F 0
10 RF Resume Flag (386+ only)
11 VM Virtual Mode Flag (386+ only)
12 AC Alignment Check (486SX+ only)
13 VIF Virtual Interrupt Flag (Pentium+)
14 VIP Virtual Interrupt Pending (Pentium+)
15 ID Indentification (Pentium+)
MSW - Machine Status Word (286+ only)
Bit # Acronym Description
0 PE Protection Enable, switches processor between
protected and real mode
1 MP Math Present, controls function of the WAIT
instruction
2 EM Emulation, indicates whether coprocessor functions
are to be emulated
3 TS Task Switched, set and interrogated by coprocessor
on task switches and when interpretting coprocessor
instructions
4 ET Extension Type, indicates type of coprocessor in
system
5-30 Reserved
31 PG Paging, indicates whether the processor uses page
tables to translate linear addresses to physical
addresses
Links
