Project: Pulse Generator

Introduction

   Figure 1.
A Pulse Generator as shown in Figure 1. consists of a single input and output line. A Single pulse on the input line generates eight pulses on the output line as shown in Figure 2. The output pulses begin on the falling edge of the input pulse. 

   Figure 2.

Flow Chart

   Figure 3.
The Flow Chart as shown in Figure 3. consists of four states, START, PULSE, DELAY, and HALT. On power on the circuit enters the HALT state with the Pulse Counter Cleared. When the input line goes high the circuit enters the START state and remains there until the input line goes low. The circuit then enters the PULSE state. The output of the PULSE state increments the Mod-8 Counter. The circuit then enters the DELAY state in which the value of the counter is checked. If the counter is not zero the circuit loops back and outputs another pulse. This continues until the counter is zero and then the circuit enters the HALT state, in which it remains until the Input line goes high for another input pulse.

Logic Diagram

As seen from the flow chart the circuit has four states. To simplify matters each state will be represented by one flip-flop. The START state will then be represented by the START flip-flop ON and the PULSE, DELAY and HALT flip-flop as OFF.

Start State

   Figure 4.
The START flip-flop will be set if the circuit is in the HALT state and the input line is high. It will remain set as long as the input line is high.

Pulse State

   Figure 5.
The PULSE flip-flop will be set if the circuit is in the START state and the input line goes low OR if the circuit is in the DELAY state and the counter is not zero.

Delay State

   Figure 6.
The DELAY flip-flop will be set if the circuit is in the PULSE state.

Halt State

   Figure 7.
The HALT flip-flop will be set if the circuit is in the DELAY state and the Counter is zero. It will remain set as long as the input line is low.

Counter

   Figure 8.
The Counter will increment after each Pulse and C=0 will be high when all flip-flops of the counter are zero.

I/O Circuits

   Figure 9.
The PWR pulse resets all flip-flops and sets the HALT flip-flop. In the worst case the Input Line must remain high for one period of the clock pulse.