David L. Andreatta
Near Denver, CO
(303) 926-1476, dandreat@earthlink.net
Education
B.S., Colorado
State University 1987
Major: Electrical
Engineering
Minor: Computer
Science
Experience
Andreatta
Engineering; Erie, CO
Proprietor / Sr. Principal Engineer /
Consultant
November
2001 through Present
August 2002
through Present: Provide contract services to local aircraft repair facilities,
Vector Air, Inc. and Aero Systems, Inc., to supply premium
avionics, instrument, and electrical systems design and integration for
certificated and experimental aircraft. Recent / current projects include a
complete communications and navigation radio stack for a light Cessna; a
complete electrical, instrument, and avionics package, with a custom panel, for
an experimental aircraft; and integration of a new IFR GPS within an autopilot
equipped Beech Bonanza. Suite of services includes: custom panels and harnesses,
Mil-Spec wiring, ARINC bus integration, bracket and rail fabrication, diagrams
in AutoCAD, IntelliCAD, and OrCAD, “grounding and shielding” training, and all
necessary interaction with FAA for inspection and field approval. (Limited
Repair Station Certificate pending.)
March 2002
through November 2002: Lead Senior Architect / Systems Engineer developing a
USB 1.1 / 2.0 interface for a high resolution CCD imaging system. Defined top
level system architecture and system requirements specification for all electronics,
USB target firmware (8051), host software driver, and Xilinx FPGA for SDRAM
control and intelligent image transfer buffer management. Completed circuit
design and schematic entry in OrCAD Capture. Retained as advisor on high-speed
board layout, bring-up, and integration topics.
Mindspeed,
Inc. (formerly Conexant Systems, Inc.); Boulder, CO
Sr.
Staff Product Applications Engineer / Systems Engineer
June 2000
through October 2001 (Resigned to
pursue full time consulting.)
Designed a
dual OC-12/48 6U CPCI Line Card, with Quad Gig-E fiber interconnect and dual
ring SONET framing / optics, as a reference design for a new IC family
implementing “SRP”. Spatial Reuse
Protocol is a new complex Media Access Control (MAC) protocol developed by
Cisco Systems, Inc. (Resilient Packet Ring (RPR), IEEE 802.17) Assisted in high
speed and PECL / CML portions of board layout and managed the transition
through fabrication, assembly, and board bring-up. (Note: This design was
profiled as the “Centerfold“
in the March 2002 issue of “Printed Circuit Design” magazine.) Consulted
on design of OC-192 version of board, including specialized decoupling scheme.
Provided principal contact support for the Mindspeed SRP product line
internationally; including architecture / systems design, Verilog FPGA design
for specialized POS (Packet Over SONET) interface, board design,
troubleshooting, training, general QA, and development of Verisity and Verilog
verification suites for situation specific simulation.
NxNetworks (formerly Netrix Corporation);
Longmont, CO
Principal Telephony Engineer
November
1998 through April 2000 (Plant Closure)
Integrated a
SiproLab implementation of the G.729A (CS-ACELP) voice compression algorithm
into the Netrix Exchange 2200 series voice / data switch providing a second
algorithm for standards based Voice over IP (VoIP) interoperability on H.323
and H.225. Development involved providing a wrapper for the “off the shelf”
compression engine in TI’s TMS320C5X assembly language on multi processor DSP
voice cards. Concurrently modified and enhanced higher layer switch support and
routing software in ‘C’ for Motorola 68030, 68360 “PowerQUICC”, and Intel
Pentium (under VxWorks). Previously responsible for design and implementation
of a packetized G.711 speech coding algorithm, on the same platform, allowing
Netrix its first foray into standards based VoIP!
Trained,
coordinated, and supervised several contractors on delay minimization, echo
cancellation, and SNMP projects; along with the lead role on a Compact PCI
based four channel voice card. Generally responsible for development and
enhancement of major new software and hardware features for the Netrix 2200
series “Network Exchange Access Switch” involving both hardware and software
design. This included creation of associated documentation, market research for
requirements derivation, handoff to test / manufacturing, and pre / post sales
support. Development, configuration, and test utilizing the multi-protocol
routing and translation capabilities of the 2200 series has fostered a general
working knowledge of PBX T1/E1, FXS, FXO, E&M, ISDN PRI/BRI, Frame Relay,
Internet Telephony, H.323, Microsoft Netmeeting, TCP/IP, UDP/IP, and IP Routing
Protocols.
Advanced Hardware Architectures; Pullman,
WA
Senior Systems Engineer
July 1996
through July 98 (Plant Closure)
Shared the
technical lead position on a joint systems / analog engineering team
responsible for competitive product characterization, definition, and design of
a family of analog front end (AFE) circuits, and an associated digital
interface, for use with a general purpose communications processor (specialized
VLIW DSP, under parallel development) to implement various modem protocols;
xDSL, ISDN, T1/E1, cable, etc. Characterization was to include clock recovery
partitioning, ADC and DAC type selection (Sigma Delta, etc.) and resolution,
gain control loop parameters, and channel modeling. Assembled and administered
an ADSL (DMT) mini‑net with two Pentium machines and a pair of Aware X200
Access Routers; configured as both routers and bridges; over a makeshift POTS
circuit as a platform to facilitate first order characterization and analysis
work.
Generally responsible
for specification of new IC products for the data coding, data storage, and
communications industries. Develop
systems architecture and design framework in VHDL with Mentor toolset utilizing
custom, semi-custom and standard cell ASIC flows. Perform tradeoff analysis, including overall bandwidth and
automation requirements. Consult,
across product lines, on motor control, host interface (SCSI, ATAPI, 1394,
etc.), forward error correction, and EMI issues. Work with customers to refine product specification and support
design-in of our IC products. Develop technical documentation including
published specifications, errata and application notes.
Exabyte Corporation; Boulder, CO
Senior Engineer
August
1992 through June 1996
Technical
lead on a team of five ASIC engineers. Coordinated design, development, and
testing of a two chip, dual track, seventy thousand gate, helical scan tape
chip set including ECC, DRAM buffer manager, (de)compressor, (de)serializer,
and (de)formatter. Personally coded and synthesized ECC e-ncoder, physical
formatter and serializer sections. Previous generation design was converted
from a Mentor Graphics netlist to Verilog HDL / Synopsys as a starting point
for modification and enhancement. Formerly responsible for controller
engineering in the Advanced Technologies group where specifications and designs
for the next generation of helical scan tape products were conceived. Developed new features and enhancements for
the current line of 8mm helical scan tape backup products. Also responsible for debugging / enhancement
of SCSI hardware and firmware.
Developed unique high-speed interprocessor communications channel, AMD
to Motorola. (Note: technique was published as an Applications Note.)
COBE Laboratories, Inc.; Arvada, CO
Cardiovascular Electronics Engineer
March
1988 through August 1992
Responsible
for structured analysis / design and implementation of control firmware for
autologous blood salvage system including specialized user interface
electronics drivers and multi-motor servo systems. Developed single-chip VME bus interface for embedded control
processor system. Designed
microcontroller data acquisition board and control software for ultrasonic
fluid level monitor. Successfully
completed implementation of operational firmware for a microcontroller based
time / temperature data logging and visualization module for surgical use.
WESTOR, Inc.; Broomfield, CO - Winchester
Disk Systems Repair and Data Recovery
Research and Development Engineer
October
1987 through March 1988
Successfully
completed design, implementation, and testing of universal servo disk
writer. Developed associated software
package for control of pattern storage, memory upload / download, programmable
spin speed, and head positioning systems.
Colorado State University, Fort Collins,
CO; Dept. of Electrical Engineering
Senior Design Project
August
1986 through May 1987
Responsible for design and implementation of Block-Kalman filtering algorithms for restoration of digital images corrupted with Gaussian noise and LSI blur.
Part
Time Engineering Consultant
1985 through
October 2001
Design and
implementation of custom hardware, IC, software, and mechanical systems for
various embedded control applications. Successfully
developed “compatible” BIOS for a line of single board computer systems. Designed and built DTMF control module for
power source switching, automated Morse identification, and access control
within a VHF voice repeater system.
Provide CAD / drafting, precision machining, and welding services for
development of various electromechanical devices and prototypes.
Retained by CSU,
Fort Collins, CO; Dept. of Chemistry; August 1986 through October 1987:
Project Engineer; responsible for design, construction, and debugging of
optics, hardware, and software involved in a multi-laser, multi-channel flow
cytometer data acquisition system.
Successfully implemented and tested high speed DMA control circuitry,
driver, and related DNA cell cycle analysis software. Developed low noise photo-multiplier tube amplifier and
associated printed circuit board.
Designed and built computer controlled shutter driver system for
photo-bleaching and photon counting process.
Special training
“Assertion
Based Verification for SOC”, Verify2002
“Grounding
and Shielding” and “Circuit Design to Reduce EMI”, Dr. Tom Van Doren
Graduate
Studies in Communications Topics, University of Idaho, Dept. of Electrical
Engineering
Advanced
Digital Communications, Bernard Sklar
Aeronautical
Engineering Topics: electrical, instrument, and fuel systems, fabric covering,
etc.; EAA
“Rapid
Product Development”, Reinertsen & Associates
“Verilog
HDL”, “Design For Synthesis / Synopsys”, Widman Associates
SCSI Design
and Implementation, Zadian Technologies
Design of
Experiments Using Statistical Methods, QINAS Inc.
Yourdon
Structured Analysis, Yourdon Structured Design, Yourdon, Inc.
EMC Design
Techniques, Don White Consulting Group
References
References
available upon request.