Andreatta Engineering

Current / Past Projects
A look at some Andreatta Engineering and David Andreatta's active and completed projects.

As much of our work is covered by confidentiality restrictions (which we take very seriously!), items on this page are limited to those which have already been publicly announced and/or are now available to the public. We may also include "work in progress" information referring only to components and information used within the design without revealing information about the client. In such a case, no strategic product information will be included so as to protect the clients' plans for release and deployment. Andreatta Engineering will never disclose confidential intellectual property, detailed design information, or product deployment information without explicit written permission from its clients. As such, much of the information you will see here is already publicly available via other means. It is collected here only to illuminate the contributions of Andreatta Engineering, or the personal contributions of David Andreatta while active as a permanent employee of the associated company.

Current Activity:

Spacecraft Systems Control Circuitry:

Interested in space exploration and it's technology? Yup, us too! Andreatta Engineering has been recently retained for a series of development efforts on some follow-on technology initially used in NASA's Deep Impact program for comet exploration. As a result, we've contributed to rad-tolerant FPGA development on these two programs: NPOESS Preparatory Project and Orbital Express Demonstration

We're currently (Q2 - Q4, 2004) developing a mixed-signal circuit card for "housekeeping" (temperature & voltage measurement, power supply and heater control, etc.) and helping with the test system (GSE) and instrument control processor board for this mission: AIM-CIPS

Can't say much more right now, but let's just say we'll soon have some technology flying in space! Watch this spot for future announcements and project or launch schedule information as it becomes public... How exciting!

Also, don't forget to check out some of our projects in aircraft subsystem design! There is some interesting work happening in that area as well!

Recent Past Projects:

USB 2.0 / 1.1 Interface for a High Resolution CCD Imaging Device:

Andreatta Engineering was recently retained by one of its associates in the capacity of systems engineer, lead architect, and board design. In conjunction with client and associate, we completed the Systems Requirements Specification - which includes the high level architecture definition for system electronics; the FPGA based I/O, SDRAM, and buffer manager; system control firmware; and USB host driver software. While detailed design and implementation of the FPGA, firmware, and host driver was handled by the prime contractor, Andreatta Engineering completed the circuit and board design in OrCAD Capture. We were also engaged in a support and advisory role as the board design transitioned to layout, and detailed implementation of the rest of the system was completed.

Here are some links to the core technologies, references, and tools:

http://www.usb.org/
Xilinx Spartan IIe FPGA's
Cadence OrCad Capture
Cypress EZ-USB FX2

Resilient Packet Ring - Spatial Reuse Protocol (while employed at Mindspeed Technologies):

David Andreatta was employed as an Applications Engineer, supporting design in of Mindspeed's OC-12/48 Spatial Reuse Protocol IC. Included in this role was systems engineering for deployment of the product within customer equipment internationally, international design assistance, troubleshooting, creation of "situation specific" IC simulation and verification suites, advice and support to the in-house systems engineering team active in firmware and driver development, creation / maintenance of the documentation suite, and creation of a reference design - for use by customers as a starting point for SRP line card design.

The reference design could best be described as "a dual OC-12/48 6U CPCI Line Card, with Quad Gig-E fiber interconnect and dual ring SONET framing / optics". Developed on an extremely aggressive schedule while performing the other duties of Applications Engineer, the challenges of multiple logic families and system voltages, clocks and signals up to 2.5 GHz, and use of "in current development" OC-48 framer IC's and driver software all gave Dave a great sense of accomplishment upon its completion!

This CPCI line card reference design was recently profiled as the Centerfold in the March issue of "Printed Circuit Design" magazine! Have a look at that with a click on the thumbnail below.

And, a look at the reference documentation suite: CX29950 Documents

Here are some links to the core technologies, references, and tools:

IEEE Resilient Packet Ring Working Group
RFC 2892
Resilient Packet Ring Alliance
Cisco's Dynamic Packet Transport (DPT)

This page last updated on November 9, 2004.