OBJECTIVE:
A logic design position or a logic design verification position that will provide a challenge and an opportunity for growth.

EDUCATION:
University of New Hampshire, Durham, New Hampshire (Sept 2001 - Present)
MBA - Expected June 2004

University of St. Thomas, St. Paul, Minnesota (Sept. 1993 - June 1997)
MS Software Engineering
Cumulative GPA: 4.0 on a 4.0 scale

University of Minnesota, Minneapolis, Minnesota (Sept. 1992 - March 1993)
VLSI Design I and VLSI Design II courses (graduate level)

Minnesota State University, Mankato, Minnesota (Sept. 1987 - June 1991)
BS Electrical Engineering (ABET accredited), Cum Laude
Cumulative GPA: 3.4 on a 4.0 scale

Winthrop Public Schools, Winthrop, Minnesota (Sept .1974 - June 1987)

EXPERIENCE:
Enterasys Networks, Inc, Rochester, New Hampshire
Design Engineer & Design Verification Engineer (Dec. 1998 - Present)

• Currently working on the next generation SmartSwitch 2200 & 6000 series products.
• Responsible for a large part of the design in one of the four ASICs. Wrote reusable synchronous and asynchronous FIFOs that are being used by the entire design team. Have played a significant role in guiding the architecture of the project. Have assisted many of the other design team members with architecting their pieces of the design and answering Verilog related questions. Synthesized the design using Synplicity and FPGA Express targeting Xilinx Virtex FPGAs. The design will be going into an ASIC in the future with an aggressive clock speed.
• Responsible for the verification environment of another of the four ASICs. Have written a model of the ASIC, input drivers to the various ports, and checkers to automatically compare the output data of the ASIC against the output data of the model. Tests are written in Verilog (for some ports) and/or C code (for the PowerPC 750 port).

Verification Engineer (Nov. 1997 - Nov. 1998)

• Verified SmartSwitch 2200 & 6000 series ASICs. Wrote PowerPC and i960 code as part of the verification effort. Performed all JTAG testing. The four ASICs and PCB had no respins for functional problems. Performed all of the gate-level simulations.

Cray Research, Inc., Chippewa Falls, Wisconsin (6 years)
Design Verification Engineer (May 1994 - October 1997)

• Named Formal Verification Technical Leader. Formally verified some of the SN1 router ASIC design with Lucent Technology's FormalCheck software.
• Ported the SN0 (Origin 2000) router testbed to be used for SN1 router design verification. Supervised student interns who assisted in porting the tests.
• Developed testbed for IEEE1159.1 JTAG controller on SN1 project. The testbed had auto-checking of results and supported IBM LSSD testing.
• Developed the simulation testbed for two of the VLSI ASICs for the follow-on system to the T90 parallel/vector supercomputer system. Testbed was written in an in-house simulation language (very similar to C) for use with an in-house simulator, and had the ability to auto-check the results with expected results.
• Developed the Verilog simulation testbed for the memory controller VLSI ASIC on the T3E massively parallel supercomputer system. Testbed auto-checked the ASIC’s results with expected results. Wrote tests for this ASIC as well as the CPU controller and router ASICs.

Systems Test Engineer (Nov. 1991 - April 1994)

• Responsible for checkout and troubleshooting of modules and systems on the C90 and T3D supercomputer systems and on the IOS-E subsystem. Wrote a number of OpenWindows utilities to speed up the checkout process. Also wrote a T3D diagnostic in DEC assembly language.

CERTIFICATES:
Registered Engineer-in-Training (EIT).

SKILLS:
Verilog, Verilint, Virsim, FPGA Express, Synplicity, Spice, Smalltalk, Unix/Linux, C, Assembly, FormalCheck, Perl, and FrameMaker.

INTERESTS:
Enjoy playing piano and reading. Sports include basketball, biking, racquetball, skiing, and tennis.

REFERENCES:
References are available upon request.