Architectural Design/Analysis
Analyze system architecture and performance throughput. Recommend ASIC/system architecture to meet customer cost, performance, and schedule requirements.
ASIC/System Design Partitioning
Partition system design into multiple ASICs or as ASIC module partitions.
Design Environment Migration/Consulting
Consult on ASIC or system development environments or migration path to more efficient design environments. Maximize customer’s return on investment.
Project Schedule Analysis
Analyze resource loading, critical paths, design process. Provide recommendation on efficient scheduling.
Design Simulation and Verification
Simulate ASIC designs at the module, IC, or system level. Verify interoperability between components through integrated system simulation. Analyze design specifications, verify implementation against design specifications, provide feedback and recommendations.
HDL Model Creation
Develop models of standard components, microprocessor bus interfaces, or ASIC modules in Verilog or VHDL for use in ASIC or system simulation/verification.
ASIC Design Porting
Convert ASIC design from one technology/geometry to another. Use synthesis tools to re-target to a different technology library.
ASIC Macro-cell Development
Develop macro-cell functions to be used as ASIC building blocks within a highly integrated ASIC design.
Synthesis/Scripting
Synthesize HDL code to target technology. Develop synthesis scripts and automating synthesis process.
Analyze system architecture and performance throughput. Recommend ASIC/system architecture to meet customer cost, performance, and schedule requirements.
ASIC/System Design Partitioning
Partition system design into multiple ASICs or as ASIC module partitions.
Design Environment Migration/Consulting
Consult on ASIC or system development environments or migration path to more efficient design environments. Maximize customer’s return on investment.
Project Schedule Analysis
Analyze resource loading, critical paths, design process. Provide recommendation on efficient scheduling.
Design Simulation and Verification
Simulate ASIC designs at the module, IC, or system level. Verify interoperability between components through integrated system simulation. Analyze design specifications, verify implementation against design specifications, provide feedback and recommendations.
HDL Model Creation
Develop models of standard components, microprocessor bus interfaces, or ASIC modules in Verilog or VHDL for use in ASIC or system simulation/verification.
ASIC Design Porting
Convert ASIC design from one technology/geometry to another. Use synthesis tools to re-target to a different technology library.
ASIC Macro-cell Development
Develop macro-cell functions to be used as ASIC building blocks within a highly integrated ASIC design.
Synthesis/Scripting
Synthesize HDL code to target technology. Develop synthesis scripts and automating synthesis process.