OGI EE564/664: High Speed Digital Interconnect

      

Description

You will learn to analyze and design inter-chip interconnect circuits for high speed digital applications. Upon completing the course, you will possess the necessary skills to implement interconnect designs for multiple gigabits per second operation.

Instructor Howard Heck
e-mail howard.heck@comcast.net
Phone 503-264-7831
Textbook

S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience),  2000, 1st edition, ISBN 0-471-36090-2.

Grading

 20%

4 homework sets

 20%

Midterm

 25%

Final

 25%

Project

 10%

Weekly Feedback

S/W Tools PSpice or some other variant of Spice.
Matlab or MathCad may also be of use.

Syllabus

Chapter Topic Slides
1 - Introduction 1-1 Overview
1-2 Trends & Challenges
1-3 Interconnect Technology
2 - Transmission Line Basics 2-1 Transmission Line Theory
2-2 Basic I/O Circuits
2-3 Reflections
2-4 Parasitics & Loading
2-5 Modeling & Simulation
2-6 Measurement Equipment
2-7 Time Domain Reflectometry
3 - Analysis Techniques 3-1 Lattice Diagrams
3-2 Bergeron Diagrams
4 - Metrics 4-1 Synchronous Timing
4-2 Signal Quality
4-3 Source Synchronous Timing
4-4 Embedded Clock Timing
4-5 Modern Design Methodology
5 - Advanced Transmission Lines 5-1 Losses
5-2 Intersymbol Interference (ISI)
5-3 Crosstalk
5-4 Frequency Domain Analysis
5-5 S-Parameters
6 - Multi-Gb/s Signaling 6-1 Projections, Limits, & Barriers
6-2 Differential Signaling
6-3 Equalization
6-4 Modulation

Course Schedule

Class
Topic(s)
Key Concepts
Reading
Problems
1
1-1, 1-2,
1-3, 2-1
Transmission line impedance & velocity
Chapters 1 & 7
Set #1
Due [5]
2
2-2, 2-3
Load lines, simple I/O models, and reflections
Chapter 2
Appendix A
 
3
2-4, 2-5
Capacitance & inductance effects
Spice.
   
4
2-6, 2-7
Time domain reflectometry
Chapter 11 (except 11.8)
 
5
3-1, 3-2
Lattice & Bergeron diagrams
Motorola AN 1406
Set #2
Due [9]
6
4-1, 4-2, 4-3
Synchronous timing analysis, signal quality metrics, & source synchronous timings
Chapter 8.1
Chapter 9.2
 
7
4-4, 4-5
Derived clock timings & Modern design methodology
Chapter 8.2
Chapter 9
 
8
5-1, 5-2
 
Conductor & dielectric losses
Intersymbol interference
Chapter 4.1
Appendix C
Chapter 4.4
Set #3
Due [12]
9
5-4
Reflection coefficient, input impedance, load impedance
   
10
5-5
Vector network analyzer, S- parameters, ABCD parameters
Chapter 11.8
 

 

 

Additional References

  • W. Dally & J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998, 1st edition, ISBN 0-521-59292-5. (Course text from 2000)

  • H. Johnson and M. Graham, High-Speed Signal Propagation: Advanced Black Magic, Prentice Hall, 2003, 1st edition.

  • R.E. Matick, Transmission Lines for Digital and Communication Networks, IEEE Press, New York, 1995, ISBN 0-7803-1121-3. (Classic text on transmission lines.)

  • R. Poon, Computer Circuits Electrical Design, Prentice Hall, Englewood Cliffs, NJ, 1995, ISBN 0-13-213471-3. (Course text from  1999)

  • Ramo, Whinnery, and Van Duzer, Fields and Waves in Communication Electronics, John Wiley & Sons, New York, 2nd edition, 1985, ISBN 0-471-871130-3.

  • H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990, ISBN 0-201-060080-6.

  • B. Young, Digital Signal Integrity, Prentice-Hall PTR, 2001, 1st edition, ISBN 0-13-028904-3.

  • H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR, Englewood Cliffs, NJ, 1993, ISBN 0-13-395724-1.

  • W.R. Blood, MECL System Design Handbook, Motorola, Inc., 4th edition, 1988.

  • S. Dabral and T. Maloney, Basic ESD and I/O Design, Wiley Interscience, New York, 1998, ISBN 0-471-25359-6.

  • J. Buchanan, Signal and Power Integrity in Digital Systems: TTL, CMOS, & BiCMOS, McGraw Hill, New York, 1996, ISBN 0-07-008734-2.

  • P. Magnusson, G. Alexander, V. Tripathi, Transmission Lines and Wave Propagation, 3rd edition, CRC Press, 1992, ISBN 0-8493-4279-1.