John Alan Swensen
© John A. Swensen 2014. All rights reserved.
I have over thirty-one years experience in analyzing,
architecting, designing, managing, consulting, and teaching about
computer systems and software, including twenty-five years of
analysis and architecture, twenty-one years of hardware design,
twenty-six years of software design and programming, forteen years of
microprogramming, three years of lecturing and course
development, and six years of management.
I am educated in computer science with a Ph.D. in computer architecture.
My project involvement has included project management,
processor design management,
validation management, processor development,
validation software tool development,
analyzing existing designs and recommending improvements,
architectures, and firmware for patent and copyright
infringement litigation, architecting and specifying machine
organizations for implementation by other groups, stepping
into the middle of projects to complete and deliver designs,
post-project support and enhancements, and taking projects
from proposal, through implementation, to customer delivery
I have written and reviewed research papers, business plans,
project proposals, technical reports, system analyses,
system design documents, principles of operation,
verification plan specifications, technical reports, and patents.
I have written employee evaluations for annual performance appraisals.
I am experienced in course development and lecturing
for industrial and university courses (both undergraduate and graduate).
I have mentored students to win a supercomputer applications contest.
I have contributed substantially to the architectures of
SPARC Version 9, the ETA-10 follow-on vector and scalar
processors, the first ray-tracing hardware architecture,
several real-time error-correcting systems,
proprietary multiprocessor architectures,
extensions to existing architectures,
and switching networks.
I architected and implemented all aspects of
an extremely low-cost, parallel,
proprietary architecture for hardware input-output processing.
I, also, architected and implemented a high-performance accelerator
for RSA and Elliptic Curve Cryptography.
I have specified the micro-architectures for super-scalar
SPARC implementations, an ETA-10 follow-on processor,
and several graphics processors.
I have designed and implemented
design automation tools,
logic verification tools,
architectural verification coverage tools,
CPU simulators, memory system simulators,
switching network simulators, instruction simulators,
routing tools, wiring tools, micro-assemblers,
data-analysis tools, graphics systems (both two-dimensional
and three-dimensional), encryption/decryption systems,
verification programs, and microprograms for 2901-based and
I have implemented several run-time operating systems for embedded systems.
I have implemented RSA and Elliptic Curve encryption/decryption algorithms,
both in software and in firmware running on special-purpose processors.
I have hand-tuned algorithms for optimal execution on specific platforms,
including arithmetic algorithms for super-scalar SPARC,
error-correction decoding algorithms for proprietary hardware,
logic optimization software for computers with limited memory,
embedded software for high-reliability systems,
and encryption/decryption algorithms for microprocessor implementations.
I have developed software using UNIX, Linux, Cygwin,
Windows 7, Windows XP, Windows NT, Windows 2000, Sunview, X-11, C, C++,
FORTRAN, Pascal, Icon, and other high-level languages,
assembly language (SPARC, VAX, PDP-11, 8080, Z80, x86,
8051, 68000, AN/AYK-14), microcode (2901, as well as many proprietary
micro-architectures, including horizontal and vertical
I have designed and implemented
several proprietary error-correcting machines,
graphics processors, camera controllers,
embedded controllers, and accelerators for Elliptic Curve Cryptography .
I designed the scalar processor for the ETA-10 follow-on.
I have designed several Array Built-In Self Test (ABIST) circuits.
I have designed hardware using CMOS FPGAs, CMOS standard-cell,
CMOS gate-arrays, PALs, 2901-based, ECL, TTL, ALS, AS, LS, S, Valid,
Synopsys. I have extensive experience debugging my own and
others' designs, in environments ranging from verification
programs running on simulators to logic analyzers and
oscilloscopes on actual hardware.
3/2013-present: Principal Engineer, Security Architect/Design, Boeing Secure Computing Solutions,
I am responsible for the design of secure computing hardware and software for high-performance embedded computing.
I have developed software to characterize various security functions
on a secure computing integrated circuit.
I managed the project to develop test fixtures and software
to facilitate security function characterization,
completing the project ahead of schedule.
I developed a side-channel analysis laboratory, using equipment and software
developed by Cryptography Research, Inc., and lead the effort to analyze hardware and software implementations
for side-channel leakage, using techniques such as Simple Power Analysis (SPA)
and Differential Power Analysis (DPA).
I used analytical results from the side-channel analysis laboratory
to modify hardware and software implementations to be more resistant to side-channel attacks.
I hold an active security clearance.
5/2001-2/2013: Group Lead, Processor Development, CPU Technology,
I am implemented firmware for Elliptic Curve Cryptography,
running on a hardware accelerator that I designed and implemented.
During this development process,
I, also, designed and implemented an assembler
for this accelerator, and supervised the verification of the hardware design.
I have managed a group of processor designers and validation engineers
responsible for implementing and validating modernized,
compatible microprocessors for mission-critical applications.
In addition to implementing several compatible processors,
I have designed and implemented new parallel processor architectures,
as well as architectural extensions
to existing microprocessor architectures to support larger address spaces,
memory management, and modern compiler development.
I have added language extensions and other enhancements to a number of
proprietary design automation tools for logic design and processor verification,
and I have designed and implemented new tools
to further automate and streamline the design process.
I have written thousands of lines of embedded software for
My duties have included visits to customer sites for demonstrations of our
4/2000-4/2001: Manager, HAL Computer Systems, Inc.,
I managed a group of hardware verification engineers,
designing assembly-language and verilog-language tests for
the CPU of a high-performance SPARC microprocessor.
I architected several verification tools, including a tool for measuring
the architectural coverage of a suite of verification programs.
This 30000-line C++ program was implemented by me and members of my group
over a four month period.
My duties include project management, scheduling,
verification test strategy and test design, recruiting,
and employee evaluation.
While performing these duties, I also implemented over 3500 verification
programs which exposed over a dozen new bugs in a relatively mature design.
9/98-3/2000: Consultant, HAL Computer Systems, Inc.,
I debugged and enhanced a trace-driven architecture
simulator written in C++. I designed and implemented a
series of test programs for verification and validation of
the architecture simulator for correspondence with the
proposed hardware implementation. I designed and
implemented several tools for analyzing and displaying
performance data on web pages.
9/97-9/98: Staff Software Design Engineer, Cirrus Logic, Inc.,
I proposed, designed and implemented a cycle-accurate
software simulator of a heterogeneous, general-purpose
multiprocessor, using the C programming language and Unix
tools. I designed and implemented substantial parts of this
multiprocessor, including caches, bus-controllers, and
global communication interfaces. The designs were specified
in the Verilog language and made use of Synopsys compilers
to target both CMOS FPGA and full-custom CMOS
implementations. I also designed and wrote assembly code
for execution on several different types processors. In
addition, I have provided consultation to other members of
the project team in areas of computer architecture, software
design, and programming methodologies.
12/95-: Expert Witness, The Chatham Group, Los Altos,
I provided technical advice and testimony for a firmware
copyright infringement case involving commercial audio
cards. I performed a clean-room experiment in which I
reverse-engineered several DSP commands, having access only
to the audio card and a software developer's kit provided by
the manufacturer. I also analyzed the firmware for several
audio cards, as well as the affidavits associated with the
case. This work culminated in my testifying as an expert
witness during the trial. This case was won upon appeal
and, in the judgment by the Court of Appeal of the Republic
of Singapore, my expert report was extensively and favorably
I have provided technical advice as an expert and potential
witness for several other cases involving manufacturing
resource planning programs, parallel processor
architectures, and digital audio cards.
4/94-11/94: Microprocessor Analyst, MicroDesign Resources,
I researched and wrote a report on embedded microprocessors,
covering all high-end, 32-bit and 64-bit embedded
microprocessors commercially available, involving extensive
analyses and comparisons of the architectures and
implementations. Information in this report was combined
with software and marketing analyses and was published under
the title ``Selecting a High-Performance Embedded
Microprocessor'' in the winter of 1995.
8/93-2/94: Technical Litigation Consultant, The Chatham
Group, Los Altos, California.
I provided technical advice for a microprocessor patent
infringement case involving virtual memory. This work
included analyses of thousands of examples of the prior art,
legal analyses of patents and depositions, transistor-level
and gate-level circuit analyses, and micro-architecture
9/90-9/93: Senior Design Engineer, HAL Computer Systems,
I was one of the founding members of haHAL Computer Systems,
where I participated in writing the original business plan
and contributed substantially to the system specifications
and architecture. I specified the original super-scalar
micro-architecture design, as well as the high-level designs
of several of the major CPU building blocks. I also
participated in the joint specification of the Version 9
enhancements of the SPARC architecture with architects at
Sun Microsystems. I designed and developed several
simulators at HAL, including a multi-computer network
simulator and several CPU micro-architecture simulators, and
I contributed towards verification of the CPU and cache
8/89-9/90: Staff System Design Engineer, Amdahl/Key
Computers, Fremont California.
I developed computer-aided design tools in support of the
development of a super-scalar CPU, and I performed board-
level signal routing analyses, developing a routing
simulator for that purpose.
6/88-6/89: Consulting Engineer in Systems Design, ETA
Systems, St. Paul, Minnesota.
At ETA Systems I reported directly to the chief architect of
the company. I had primary responsibility for the design of
a scalar processor follow-on to the ETA-10 vector
supercomputer, which offered a performance of 1.2 billion
floating point operations per second using only two chip-
types and six processor chips, altogether. I participated
in the specification of a vector supercomputer follow-on to
the ETA-10 supercomputer, contributing to the instruction-
set architecture and memory system architectures. I was
mentor to advanced students developing award-winning
supercomputer application software.
12/87: Ph.D. Dissertation: "High-Bandwidth/Low-Latency
Temporary Storage for Supercomputers".
My doctoral dissertation involved unique vector registers
that simultaneously provided extremely fast access and high
bandwidth. I also developed general-purpose register
structures which provided fast access times with an
essentially-unlimited number of registers, and I designed a
pipelined, random-access memory allowing multiple,
overlapped read and write accesses to the same memory chip.
I also developed a new mechanism for program structure
analysis, a theory of optimal pipeline design, and several
In addition to my doctoral dissertation, I co-authored the
first paper on hardware ray-tracing architectures, which is
still referenced in standard computer graphics texts. I
also developed heuristic algorithms for program instruction
scheduling for supercomputer applications, and I developed
software for computer graphics. I helped to develop
undergraduate and graduate courses taught at the University
of California at Berkeley, and I lectured for undergraduate
and graduate courses there.
9/83-5/88: Member of Technical Staff, Cyclotomics, Berkeley,
While working towards my doctorate, I worked at Cyclotomics,
an advanced-development company staffed primarily by Ph.D.
mathematicians, engineers, and computer scientists. I
developed software for cryptography and I developed
software, microcode, and hardware for error correction
devices, ranging in complexity from microprocessor-based
systems to semi-custom designs to fully-custom, state-of-
the-art systems. These systems were incorporated in optical
disks, longitudinal and helical magnetic tapes, satellite
transmission systems, and radio communications systems. I
also developed software tools and micro-assemblers for our
proprietary architectures. I developed a simulator and an
architecture for a massively-parallel-computer switching
network, and I was co-inventor of a patented, digital phase-
9/82-3/83: Engineer, Jupiter Systems, Alameda, California.
Early in my graduate studies I worked at Jupiter Systems, a
company developing computer graphics hardware. My duties
included the development of computer graphics software, as
well as the analysis of an advanced graphics processor
6/82: Master's Project: "An Experimental Graphics Terminal"
As part of my Master's project, I designed and built a high-
performance, bit-mapped graphics terminal. This terminal
supported complex graphical operations which were executed
by a microcoded graphics processor of my own design.
8/80-12/80: Development Engineer, Hewlett-Packard, Santa
At Hewlett-Packard I helped to specify the software design
of an advanced instrument test system.
6/78-12/78: Engineering Coop, John Fluke Manufacturing
Company, Everett, Washington.
During an engineering coop program, I designed a low-power,
low-electrical-noise LCD instrument display subsystem, a
descendent of which replaced the existing display subsystem.
I also designed and implemented a test strategy for the
floating point software implementation of a test instrument,
uncovering and correcting a subtle floating-point bug in the
Ph.D. Computer Science, University of California at
Berkeley, December, 1987 (Computer Architecture Major,
Software and Vision Minors).
M.S. Computer Science, University of California at Berkeley,
A.B. Computer Science, University of California at Berkeley,
J.A. Swensen and Y.N. Patt, "Hierarchical Registers for
Scientific Computers", Proceedings of the ACM International
Conference on Supercomputing, July 4-8, 1988, St. Malo, France.
J.A. Swensen, "High-Bandwidth/Low-Latency Temporary Storage
for Supercomputers, Ph.D. Dissertation, University of
California at Berkeley, Report No. UCB/CSD 87/383, December 1987.
J.A. Swensen and Y.N. Patt, "Fast Temporary Storage for
Serial and Parallel Execution", Proc. 14th Annual Symp. on
Computer Architecture, pp. 35-43 (June 1987).
M. Dippé and J. Swensen, "An Adaptive Subdivision Algorithm
and Parallel Architecture for Realistic Image Synthesis",
Computer Graphics, 18(13) pp. 149-158 (July 1984).
J. Swensen and G. Walters,
"High-Performance, Parallel Embedded Architectures Using Acalis CPU872 PowerPC Multicore",
2008 High Performance Embedded Computing Conference,
Lincoln Laboratory, Massachusetts Institute of Technology,
Lexington, Massachusetts, September 23-25, 2008.
J. Swensen and G. Walters,
"Secure, High-Performance, Parallel Embedded Architectures Using Acalis CPU872 PowerPC Multicore",
2009 Components for Military and Space Electronics Conference,
San Diego, California, February 10-12, 2009.
J. Swensen and G. Walters,
"Multi-Layered Hardware Protections for Advanced Secure Processing",
2009 DoD Anti-Tamper Conference, 9th Annual Conference,
Johs Hopkins University/Applied Physics Laboratory, Kossiakoff Center,
Laurel, MD, April 27 - May 1, 2009.
E.T. Cohen and J.A. Swensen, United States Patent 4,820,993,
"Digital Phase Lock Loop" (April 11, 1989).
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/ revised 2010 July 24