;; Emacs Mode Selection Info: -*-mode: ASM; coding: iso-latin-1-dos;-*- * ;; ******************************************************************************************** ;; File Name: Four_All.equ ;; Auther: John L. Weinrich ;; Date: 01/31/03 ;; Useage 4004 TIC-TAC-TOE Game ;; Description: ;; ;; This file defines all the equates needed by the 4004 Game ;; ;; ;; ******************************************************************************************** ;; Test constants TEST_CHAR0 equ 0AH ; Test charactor for memory test TEST_CHAR1 equ 05H ; Test charactor for memory test ;; Pass/fail indicators MEM_GOOD equ 0 MEM_BAD equ 1 INIT_HW_SUCCESS equ 0 INIT_HW_FAILURE equ 1 REPORT_SUCCESS equ 0 REPORT_FAILURE equ 1 ACTIVE equ 1 INACTIVE equ 0 DEFAULT_PLAYER equ 002H MODE1 equ 01H MODE2 equ 02H ;; RAM controls RAM_BANK_0 equ 00H ; RAM Bank 0 RAM_BANK_1 equ 01H ; RAM Bank 1 RAM_BANK_2 equ 02H ; RAM Bank 2 RAM_BANK_3 equ 03H ; RAM Bank 3 RAM_BANK_4 equ 04H ; RAM Bank 4 RAM_BANK_5 equ 05H ; RAM Bank 5 RAM_BANK_6 equ 06H ; RAM Bank 6 RAM_BANK_7 equ 07H ; RAM Bank 7 RAM_0_REG_0_CHAR_0 equ 000H ; RAM register 0, RAM CHAR 0, range 0-255 MISC_RAM_SHADOW equ 000H ; MISC port shadow storage MISC2_RAM_SHADOW equ 001H ; MISC2 port shadow storage UTILITY_0_L_RAM equ 002H ; UTILITY_0_L_RAM UTILITY_0_H_RAM equ 003H ; UTILITY_0_H_RAM UTILITY_1_L_RAM equ 004H ; UTILITY_1_L_RAM UTILITY_1_H_RAM equ 005H ; UTILITY_1_H_RAM UTILITY_2_L_RAM equ 006H ; UTILITY_2_L_RAM UTILITY_2_H_RAM equ 007H ; UTILITY_2_H_RAM UTILITY_3_L_RAM equ 008H ; UTILITY_3_L_RAM UTILITY_3_H_RAM equ 009H ; UTILITY_3_H_RAM OPTION_1_RAM equ 00AH ; Option switch #1 POR location OPTION_2_RAM equ 00BH ; Option switch #2 POR location RNG_RAM equ 00CH ; Random number generator storage location FPGA_VERSION_RAM equ 00DH ; FPGA version storage location SYSTEM_STATE_RAM equ 00EH ; System state storage location KYB_STATE_L_RAM equ 00FH ; Keyboard low state storage location KYB_STATE_H_RAM equ 010H ; Keyboard high state storage location DIS_ONOFF_CONT_H_RAM equ 011H ; Display on/off control state High storage location DIS_ONOFF_CONT_L_RAM equ 012H ; Display on/off control state low storage location GAME_MODE_RAM equ 013H ; Game mode storage location SPEAKER_LEVEL_RAM equ 014H ; Speaker level storage location POS1_RAM equ 015H ; Game board position #1 state POS2_RAM equ 016H ; Game board position #2 state POS3_RAM equ 017H ; Game board position #3 state POS4_RAM equ 018H ; Game board position #4 state POS5_RAM equ 019H ; Game board position #5 state POS6_RAM equ 01AH ; Game board position #6 state POS7_RAM equ 01BH ; Game board position #7 state POS8_RAM equ 01CH ; Game board position #8 state POS9_RAM equ 01DH ; Game board position #9 state PLAYER_1_MARK_RAM equ 01EH ; Player #1 Mark location PLAYER_2_MARK_RAM equ 01FH ; Player #1 Mark location PLAYER_MARK_RAM equ 020H ; Player #1 Mark location PLAYER_TURN_RAM equ 021H ; Player turn location GAME_STATUS_RAM equ 022H ; Game status storage location TURN_COUNT_RAM equ 023H ; Player turn counter storage location SKILL_STATE_RAM equ 024H ; Slill level storage location PLAYER_START_RAM equ 025H ; Player Start location PLAYER_1_RAM equ 030H ; Player #1 name RAM storage begin location PLAYER_2_RAM equ 050H ; Player #2 name RAM storage begin location ;; RAM init values INIT_MISC_RAM_SHADOW equ 000H ; MISC port shadow initialization value INIT_MISC2_RAM_SHADOW equ 000H ; MISC2 port shadow initialization value INIT_DIS_ONOFF_CONT_H equ 0000B ; Display on/off high control init value INIT_DIS_ONOFF_CONT_L equ 1111B ; Display on/off low control init value POS_NONE equ 00H ; Game position init value PLAYER_X_CHAR equ 001H ; X charactor PLAYER_O_CHAR equ 002H ; O charactor PLAYER_NONE_CHAR equ 000H ; None charactor PLAYER_1_TURN equ 001H ; Player #1 turn charactor PLAYER_2_TURN equ 000H ; Player #2 turn charactor GS_NONE equ 000H ; Game status none GS_DRAW equ 001H ; Game status draw GS_XWIN equ 002H ; Game status X wins GS_OWIN equ 003H ; Game status O wins MAX_TURNS equ 009H ; Max number of turns SKILL_LEVEL1 equ 000H ; Skill level 1 SKILL_LEVEL2 equ 001H ; Skill level 2 SKILL_LEVEL3 equ 002H ; Skill level 3 SKILL_LEVEL4 equ 003H ; Skill level 4 PLAYER_1_START equ 001H ; Player #1 start PLAYER_2_START equ 000H ; Player #2 start ;; Port addresses MISC_PORT equ 00000000B ; Port 0 SPEAKER_PITCH_PORT equ 01000000B ; Port 1 SPEAKER_LEVEL_PORT equ 10000000B ; Port 2 DISPLAY_HIGH_PORT equ 00110000B ; Port 3 DISPLAY_LOW_PORT equ 01000000B ; Port 4 KYBD_HIGH_PORT equ 01010000B ; Port 5 KYBD_LOW_PORT equ 01100000B ; Port 6 MISC2_PORT equ 01110000B ; Port 7 PAGE_PORT equ 10000000B ; Port 8 RAND_NUM_GEN_PORT equ 10010000B ; Port 9 FPGA_VERSION_PORT equ 10100000B ; Port 10 ;; Page settings PAGE_1 equ 000H ; Page port page #1 value PAGE_2 equ 001H ; Page port page #2 value PAGE_3 equ 002H ; Page port page #3 value PAGE_4 equ 003H ; Page port page #4 value PAGE_5 equ 004H ; Page port page #5 value PAGE_6 equ 005H ; Page port page #6 value PAGE_7 equ 006H ; Page port page #7 value PAGE_8 equ 007H ; Page port page #8 value PAGE_9 equ 008H ; Page port page #9 value PAGE_10 equ 009H ; Page port page #10 value PAGE_11 equ 00AH ; Page port page #11 value PAGE_12 equ 00BH ; Page port page #12 value PAGE_13 equ 00CH ; Page port page #13 value PAGE_14 equ 00DH ; Page port page #14 value PAGE_15 equ 00EH ; Page port page #15 value PAGE_16 equ 00FH ; Page port page #16 value BIT_ROUTINE equ 00000001B GET_PLAYERS equ 00000010B GET_POSITION equ 00000011B CHECK_WIN equ 00000100B DIS_BRD_POS equ 00000101B GET_4004_POS equ 00000110B NO_ROUTINE equ 11111111B ;; Speaker constants SPEAKER_PITCH_279HZ equ 00H ; 279 Hz pitch SPEAKER_PITCH_298HZ equ 01H ; 298 Hz pitch SPEAKER_PITCH_319HZ equ 02H ; 319 Hz pitch SPEAKER_PITCH_343HZ equ 03H ; 343 Hz pitch SPEAKER_PITCH_372HZ equ 04H ; 372 Hz pitch SPEAKER_PITCH_406HZ equ 05H ; 406 Hz pitch SPEAKER_PITCH_446HZ equ 06H ; 446 Hz pitch SPEAKER_PITCH_496HZ equ 07H ; 496 Hz pitch SPEAKER_PITCH_558HZ equ 08H ; 558 Hz pitch SPEAKER_PITCH_637HZ equ 09H ; 637 Hz pitch SPEAKER_PITCH_744HZ equ 0AH ; 744 Hz pitch SPEAKER_PITCH_893HZ equ 0BH ; 893 Hz pitch SPEAKER_PITCH_1116HZ equ 0CH ; 1116 Hz pitch SPEAKER_PITCH_1488HZ equ 0DH ; 1488 Hz pitch SPEAKER_PITCH_2232HZ equ 0EH ; 2232 Hz pitch SPEAKER_PITCH_4464HZ equ 0FH ; 4464 Hz pitch SPEAKER_LEVEL_OFF equ 00H ; Level OFF SPEAKER_LEVEL_1 equ 01H ; Level 1 SPEAKER_LEVEL_2 equ 02H ; Level 2 SPEAKER_LEVEL_3 equ 03H ; Level 3 SPEAKER_LEVEL_4 equ 04H ; Level 4 SPEAKER_LEVEL_5 equ 05H ; Level 5 SPEAKER_LEVEL_6 equ 06H ; Level 6 SPEAKER_LEVEL_7 equ 07H ; Level 7 SPEAKER_LEVEL_8 equ 08H ; Level 8 SPEAKER_LEVEL_9 equ 09H ; Level 9 SPEAKER_LEVEL_10 equ 0AH ; Level 10 SPEAKER_LEVEL_11 equ 0BH ; Level 11 SPEAKER_LEVEL_12 equ 0CH ; Level 12 SPEAKER_LEVEL_13 equ 0DH ; Level 13 SPEAKER_LEVEL_14 equ 0EH ; Level 14 SPEAKER_LEVEL_15 equ 0FH ; Level 15 ;; Display constants DISPLAY_COMMAND_MODE equ 0100B ; Display command mode & Done LED off DISPLAY_DATA_MODE equ 0101B ; Display data mode & Done LED off DISPLAY_CLEAR_CMND_L equ 0001B ; Display clear command lower nibble DISPLAY_CLEAR_CMND_H equ 0000B ; Display clear command upper nibble DISPLAY_HOME_CMND_L equ 0010B ; Display home command lower nibble DISPLAY_HOME_CMND_H equ 0000B ; Display home command upper nibble DISPLAY_CUR_ON_CMND_L equ 1111B ; Display on command lower nibble DISPLAY_CUR_ON_CMND_H equ 0000B ; Display on command upper nibble DISPLAY_CUR_OFF_CMND_L equ 1101B ; Display on command lower nibble DISPLAY_CUR_OFF_CMND_H equ 0000B ; Display on command upper nibble DISPLAY_ON_CMND_L equ 1100B ; Display on command lower nibble DISPLAY_ON_CMND_H equ 0000B ; Display on command upper nibble DISPLAY_OFF_CMND_L equ 1000B ; Display off command lower nibble DISPLAY_OFF_CMND_H equ 0000B ; Display off command upper nibble DISPLAY_FCN1_CMND_L equ 0000B ; Display function1 command lower nibble DISPLAY_FCN1_CMND_H equ 0011B ; Display function1 command upper nibble DISPLAY_FCN2_CMND_L equ 1000B ; Display function2 command lower nibble DISPLAY_FCN2_CMND_H equ 0011B ; Display function2 command upper nibble DISPLAY_MODE_CMND_L equ 0110B ; Display mode command lower nibble DISPLAY_MODE_CMND_H equ 0000B ; Display mode command upper nibble DISPLAY_CG_ADDRESS_L equ 0000B ; Display CG-RAM address lower nibble DISPLAY_CG_ADDRESS_H equ 0100B ; Display CG-RAM address upper nibble DISPLAY_DD_ADDRESS_L equ 0000B ; Display DD-RAM address lower nibble DISPLAY_DD_ADDRESS_H equ 1000B ; Display DD-RAM address upper nibble DISPLAY_LINE1_CMND_L equ 0000B ; Display set line 1 command lower nibble DISPLAY_LINE1_CMND_H equ 1000B ; Display set line 1 command upper nibble DISPLAY_LINE2_CMND_L equ 0000B ; Display set line 2 command lower nibble DISPLAY_LINE2_CMND_H equ 1100B ; Display set line 2 command upper nibble DISPLAY_LINE3_CMND_L equ 0100B ; Display set line 3 command lower nibble DISPLAY_LINE3_CMND_H equ 1001B ; Display set line 3 command upper nibble DISPLAY_LINE4_CMND_L equ 0100B ; Display set line 4 command lower nibble DISPLAY_LINE4_CMND_H equ 1101B ; Display set line 4 command upper nibble L1C1 equ 10000000B L1C2 equ 10000001B L1C3 equ 10000010B L1C4 equ 10000011B L1C5 equ 10000100B L1C6 equ 10000101B L1C7 equ 10000110B L1C8 equ 10000111B L1C9 equ 10001000B L1C10 equ 10001001B L1C11 equ 10001010B L1C12 equ 10001011B L1C13 equ 10001100B L1C14 equ 10001101B L1C15 equ 10001110B L1C16 equ 10001111B L1C17 equ 10010000B L1C18 equ 10010001B L1C19 equ 10010010B L1C20 equ 10010011B L2C1 equ 11000000B L2C2 equ 11000001B L2C3 equ 11000010B L2C4 equ 11000011B L2C5 equ 11000100B L2C6 equ 11000101B L2C7 equ 11000110B L2C8 equ 11000111B L2C9 equ 11001000B L2C10 equ 11001001B L2C11 equ 11001010B L2C12 equ 11001011B L2C13 equ 11001100B L2C14 equ 11001101B L2C15 equ 11001110B L2C16 equ 11001111B L2C17 equ 11010000B L2C18 equ 11010001B L2C19 equ 11010010B L2C20 equ 11010011B L3C1 equ 10010100B L3C2 equ 10010101B L3C3 equ 10010110B L3C4 equ 10010111B L3C5 equ 10011000B L3C6 equ 10011001B L3C7 equ 10011010B L3C8 equ 10011011B L3C9 equ 10011100B L3C10 equ 10011101B L3C11 equ 10011110B L3C12 equ 10011111B L3C13 equ 10100000B L3C14 equ 10100001B L3C15 equ 10100010B L3C16 equ 10100011B L3C17 equ 10100100B L3C18 equ 10100101B L3C19 equ 10100110B L3C20 equ 10100111B L4C1 equ 11010100B L4C2 equ 11010101B L4C3 equ 11010110B L4C4 equ 11010111B L4C5 equ 11011000B L4C6 equ 11011001B L4C7 equ 11011010B L4C8 equ 11011011B L4C9 equ 11011100B L4C10 equ 11011101B L4C11 equ 11011110B L4C12 equ 11011111B L4C13 equ 11100000B L4C14 equ 11100001B L4C15 equ 11100010B L4C16 equ 11100011B L4C17 equ 11100100B L4C18 equ 11100101B L4C19 equ 11100110B L4C20 equ 11100111B ;; Done LED controls DONE_LED_RED equ 0010B ; Set bit #2 for red DONE_LED_ON equ 0100B ; Set bit #3 for on ;; Hard reset control HARD_RESET equ 1000B ; Set bit #4 to hard reset ; Register definitions ARRAY_PTR_P reg r0r1 ARRAY_PTR_H reg r0 ARRAY_PTR_L reg r1 UTILITY_0_P reg r2r3 UTILITY_0_H reg r2 UTILITY_0_L reg r3 UTILITY_1_P reg r4r5 UTILITY_1_H reg r4 UTILITY_1_L reg r5 UTILITY_2_P reg r6r7 UTILITY_2_H reg r6 UTILITY_2_L reg r7 UTILITY_3_P reg r8r9 UTILITY_3_H reg r8 UTILITY_3_L reg r9 SCRATCH_0_P reg rArB SCRATCH_0_H reg rA SCRATCH_0_L reg rB SCRATCH_1_P reg rCrD SCRATCH_1_H reg rC SCRATCH_1_L reg rD SRC_P reg rErF SRC_H reg rE SRC_L reg rF