;; Emacs Mode Selection Info: -*-mode: ASM; coding: iso-latin-1-dos;-*- * ;; ******************************************************************************************** ;; File Name: Misc.inc ;; Auther: John L. Weinrich ;; Date: 01/31/03 ;; Useage 4004 TIC-TAC-TOE Game ;; Description: ;; ;; This file is an include file containing misc routines. ;; ;; See "4004 FPGA Design" and "4004 Software Design " documents for more detail information. ;; ;; Registers used: SRC_P, UTILITY_0_L, UTILITY_0_H, UTILITY_0_P, UTILITY_1_L, ;; UTILITY_1_H, UTILITY_1_P ;; Memory used: UTILITY_0_L_RAM, UTILITY_0_H_RAM, UTILITY_1_L_RAM, UTILITY_1_H_RAM, ;; MISC_RAM_SHADOW, DIS_ONOFF_CONT_H_RAM, MISC2_RAM_SHADOW, OPTION_1_RAM, OPTION_2_RAM, ;; FPGA_VERSION_RAM, GAME_MODE_RAM, POS1_RAM, POS2_RAM, POS3_RAM, POS4_RAM, ;; POS5_RAM, POS6_RAM, POS7_RAM, POS8_RAM, POS9_RAM, GAME_STATUS_RAM ;; Entrance parameters: None. ;; Exit parameters: Accumulator, success, failure ;; Labels used: Wait, Loop, InitSWHW, OptSwitch2Set, CheckOption2, OptSwitch1Set, ;; OptSwitch1Clear, SetMode1, SetMode2, InitGB, InitStat ;; Routines used: InitGB, InitStat ;; ******************************************************************************************** ;; ******************************************************************************************** ;; This is a simple wait subroutine ;; ;; Save UTILITY_0_P register Wait ldm RAM_BANK_0 ; Select RAM bank 0 dcl ; Send out RAM bank selection fim SRC_P,UTILITY_0_L_RAM ; Get UTILITY_0_L RAM Storage src SRC_P ; Tell UTILITY_0_L RAM it is selected xch UTILITY_0_L wrm ; Save UTILITY_0_L fim SRC_P,UTILITY_0_H_RAM ; Get UTILITY_0_H RAM Storage src SRC_P ; Tell UTILITY_0_H RAM it is selected xch UTILITY_0_H wrm ; Save UTILITY_0_L ;; Save UTILITY_1_P register fim SRC_P,UTILITY_1_L_RAM ; Get UTILITY_1_L RAM Storage src SRC_P ; Tell UTILITY_1_L RAM it is selected xch UTILITY_1_L wrm ; Save UTILITY_1_L fim SRC_P,UTILITY_1_H_RAM ; Get UTILITY_1_H RAM Storage src SRC_P ; Tell UTILITY_1_H RAM it is selected xch UTILITY_1_H wrm ; Save UTILITY_0_L ;; Do the wait thing fim UTILITY_0_P,0 ; Preset wait counter #1 fim UTILITY_1_P,0 ; Preset wait counter #2 Loop isz UTILITY_0_H,Loop ; Loop to waste time isz UTILITY_0_L,Loop ; loop again isz UTILITY_1_H,Loop ; And again ;; Restore UTILITY_0_P fim SRC_P,UTILITY_0_L_RAM ; Get UTILITY_0_L RAM Storage src SRC_P ; Tell UTILITY_0_L RAM it is selected rdm xch UTILITY_0_L fim SRC_P,UTILITY_0_H_RAM ; Get UTILITY_0_L RAM Storage src SRC_P ; Tell UTILITY_0_L RAM it is selected rdm xch UTILITY_0_H ;; Restore UTILITY_1_P fim SRC_P,UTILITY_1_L_RAM ; Get UTILITY_1_L RAM Storage src SRC_P ; Tell UTILITY_1_L RAM it is selected rdm xch UTILITY_1_L fim SRC_P,UTILITY_1_H_RAM ; Get UTILITY_1_L RAM Storage src SRC_P ; Tell UTILITY_1_L RAM it is selected rdm xch UTILITY_1_H ;; Return bbl REPORT_SUCCESS ; All done waiting, return to caller ;; ******************************************************************************************** ;; This subroutine presets the software and hardware InitSWHW ldm RAM_BANK_0 ; Select RAM bank 0 dcl ; Send out RAM bank selection fim SRC_P,MISC_RAM_SHADOW ; Select MISC port RAM shadow charactor src SRC_P ; Send out RAM charactor selection ldm INIT_MISC_RAM_SHADOW ; Get the value to initialize to wrm ; Write init data to MISC port shadow fim SRC_P,MISC_PORT ; Select MISC port src SRC_P ; Send out port selection wrr ; Preset MISC port to Shadow value ldm RAM_BANK_0 ; Select RAM bank 0 dcl ; Send out RAM bank selection fim SRC_P,MISC2_RAM_SHADOW ; Select MISC2 port RAM shadow charactor src SRC_P ; Send out RAM charactor selection ldm INIT_MISC2_RAM_SHADOW ; Get the value to initialize to wrm ; Write init data to MISC2 port shadow fim SRC_P,MISC2_PORT ; Select MISC2 port src SRC_P ; Send out port selection wrr ; Preset MISC2 port to Shadow value ;; Preset display on/off control state ldm RAM_BANK_0 ; Select RAM bank 0 dcl ; Send out RAM bank selection fim SRC_P,DIS_ONOFF_CONT_H_RAM ; Select RAM state charactor src SRC_P ; Send out RAM charactor selection ldm INIT_DIS_ONOFF_CONT_H ; Get the value to initialize to wrm ; Write init data to storage location ldm RAM_BANK_0 ; Select RAM bank 0 dcl ; Send out RAM bank selection fim SRC_P,DIS_ONOFF_CONT_L_RAM ; Select RAM state charactor src SRC_P ; Send out RAM charactor selection ldm INIT_DIS_ONOFF_CONT_L ; Get the value to initialize to wrm ; Write init data to storage location ;; Initialize game board and status settings jms InitGB jms InitStat ;; ******************************************************************************************** ;; Get state of option switches ;; ;; Set the RAM bank ldm RAM_BANK_0 ; Move RAM bank pointer to ACC dcl ; Select RAM bank ;; Read MISC port fim SRC_P,MISC_PORT ; Select MISC port src SRC_P ; Send out MISC port selection clb ; Make sure accumulator and carry are cleared rdr ; Get MISC port data ;; Check option 2 switch ral ; Move MISC option switch #2 to carry bit location fim SRC_P,OPTION_2_RAM ; Get pointer to option awitch RAM src SRC_P ; Select RAM, RAM REG, & RAM CHAR jcn C,OptSwitch2Set ; Test option switch #2 ldm 0 wrm jun CheckOption2 OptSwitch2Set ldm 1 wrm CheckOption2 fim SRC_P,MISC_PORT ; Select MISC port src SRC_P ; Send out MISC port selection clb ; Make sure accumulator and carry are cleared rdr ; Get MISC port data ;; Check option 1 switch ral ; Move MISC option switch #1 to carry bit location ral ; " " fim SRC_P,OPTION_1_RAM ; Get pointer to option switch RAM src SRC_P ; Select RAM, RAM REG, & RAM CHAR jcn C,OptSwitch1Set ; Test option switch #1 ldm 0 wrm jun OptSwitch1Clear OptSwitch1Set ldm 1 wrm OptSwitch1Clear nop ;; ******************************************************************************************** ;; Get FPGA version ;; ;; Set the RAM bank ldm RAM_BANK_0 ; Move RAM bank pointer to ACC dcl ; Select RAM bank ;; Read FPGA version port fim SRC_P,FPGA_VERSION_PORT ; Select FPGA version port src SRC_P ; Send out FPGA version port selection clb ; Make sure accumulator and carry are cleared rdr ; Get FPGA version port data fim SRC_P,FPGA_VERSION_RAM ; Get pointer to FPGA version RAM src SRC_P ; Select RAM, RAM REG, & RAM CHAR wrm ; Save FPGA version to RAM bbl REPORT_SUCCESS ; ;; ******************************************************************************************** ;; Sets the game mode in RAM ;; SetMode1 ldm RAM_BANK_0 ; Select RAM bank 0 dcl ; Send out RAM bank selection fim SRC_P,GAME_MODE_RAM ; Select mode charactor src SRC_P ; Tell RAM of selection ldm 01H ; select mode 1 wrm ; store mode bbl REPORT_SUCCESS ; All done, go back SetMode2 ldm RAM_BANK_0 ; Select RAM bank 0 dcl ; Send out RAM bank selection fim SRC_P,GAME_MODE_RAM ; Select mode charactor src SRC_P ; Tell RAM of selection ldm 02H ; select mode 2 wrm ; store mode bbl REPORT_SUCCESS ; All done, go back ;; Preset game positions ;; Set the RAM bank InitGB ldm RAM_BANK_0 ; Move RAM bank pointer to ACC dcl ; Select RAM bank fim SRC_P,POS1_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection ldm POS_NONE ; Get the value to initialize to wrm ; Write init data to storage location fim SRC_P,POS2_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection wrm ; Write init data to storage location fim SRC_P,POS3_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection wrm ; Write init data to storage location fim SRC_P,POS4_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection wrm ; Write init data to storage location fim SRC_P,POS5_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection wrm ; Write init data to storage location fim SRC_P,POS6_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection wrm ; Write init data to storage location fim SRC_P,POS7_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection wrm ; Write init data to storage location fim SRC_P,POS8_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection wrm ; Write init data to storage location fim SRC_P,POS9_RAM ; Select RAM position charactor src SRC_P ; Send out RAM charactor selection wrm ; Write init data to storage location bbl REPORT_SUCCESS ; All done, go back ;; Preset game status ;; Set the RAM bank InitStat ldm RAM_BANK_0 ; Move RAM bank pointer to ACC dcl ; Select RAM bank fim SRC_P,GAME_STATUS_RAM ; Select RAM game status charactor src SRC_P ; Send out RAM charactor selection ldm GS_NONE ; Get the value to initialize to wrm ; Write init data to storage location bbl REPORT_SUCCESS ; All done, go back