Kevin Frenette
Hardware Design Engineer
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Synopsis
Employed as a hardware digital design engineer for 13
years specializing in both FPGA and Board Level design. Experienced in all phases of new product
development from the conceptual stages to high volume production release.
Proficient in designing complex FPGAs using Verilog/VHDL, logic &
timing simulation, timing closure, high-speed PCB design and signal integrity,
directing PCB layout, hardware debug, design verification & testing,
and documentation for production.
Creative and methodical approach to a problem solving. Proven track record in leading design
teams.
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Selected
Strengths
- Hardware languages: Verilog
and VHDL.
- Hardware tools:
DxDesigner/Viewlogic, OrCAD Capture, Synplicity, Cadence Verilog-XL,
Synopsys VCS, Synopsys Virsim, ModelSimSE, Xilinx ISE, Altera Quartus, & Timing Designer.
- Active DoD Secret Clearance.
- Effective written and verbal
abilities.
- Strong organizational and
interpersonal skills.
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Education
- UNIVERSITY OF MAINE,
Orono, ME. BSEE Technology, 5/1995.
- PLYMOUTH STATE
UNIVERSITY, Plymouth, NH.
MBA, 5/2000.
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Experience
9/2002 - Present
Digital Hardware Engineer
Design digitally computed RF communication and
synthesizer technology to produce signals up to 20GHz with precise tuning,
fast switching, low phase noise, and high spurious free dynamic range. Responsible for both FPGA and Board Level
Design in all of my projects.
- Sentinel Air Defense RADAR: Designed a direct digital
synthesizer module and a waveform controller module for the Sentinel
Radar program for the U.S. Army.
These modules comprised of the Sentinel Exciter portion of the
Raytheon Radar system.
- Compass Call Program: Designed a direct digital
synthesizer module for BAE Systems as an equipment upgrade to enhance
and modernize various systems of the U.S. Air Force EC-130H Compass
Call program.
- AN/SPS-48G(V) RADAR: Designed a direct digital
synthesizer module (6U Size B VME Card) for the U.S. Navy long range
land or sea AN/SPS-48G(V) RADAR.
The design upgrade known as ROAR (Radar Obsolescence
Availability Recovery) will improve reliability, maintainability, and
availability for the Naval Sea Systems Command.
- STS-107 CANDOS Space Experiment: Key contributor in the design and
testing of an LO synthesizer module for a Low Power Transceiver (LPT)
space experiment called STS-107 Communications and Navigation
Demonstrations On Space Shuttle (CANDOS) developed with NASA
GSFC. Our LO module utilized
radiation tolerant Actel and Xilinx FPGA based transceivers. The LPT provided 28 channel GPS
receiver, 4 channels of dedicated communications through: NASA’s
Tracking and Data Relay Satellite System (TDRSS), NASA’s Spaceflight
Tracking and Data Network (STDN), Air Force Satellite Control Network
(AFSCN), and LPT-to-LPT crosslink.
All communication paths were successfully demonstrated.
- Direct Digital Synthesizer (DDS): Designed 1GHz Numerically Controlled
Oscillators (NCO) in both Xilinx Vitex5 and Virtex4 FPGAs for a low
spurious Direct Digital Synthesizer (DDS). My NCO designs may take frequency
control data either from a user module or USB2.0 device. The NCO outputs digitally encoded
sine wave data to a digital-to-analog-converter (DAC). The NCO together with a DAC creates
a DDS. Some FPGA designs
operate at FMAX of 500MHz, therefore, most logic blocks and nets are
constrained by hand using Floorplanner and FPGA Editor tools. Applications for digitally-based
broadband synthesizers include Radar Systems, Electronic Warfare
applications, precision-guided munitions, as well as high-end test
equipment for Function Generators and Waveform Generators.
- Designed
numerous System Controller cards, Radar Programming Interface cards,
and Radar Data Logging cards.
Used Xilinx Spartan 3 and Virtex4 FPGAs for these cards. Many interfaces for these cards used
WiFi 802.11g, Fast Ethernet, USB2.0, and PC Parallel Port.
10/2001 - 9/2002 CETACEAN NETWORKS Portsmouth, NH 03801
Senior Hardware Engineer
Designed system boards for the Schedule Switch Router
enabling Real-Time IP for Internet communication systems:
- Designed a 4 port DS3
interface card for the Schedule Switch Router. Completed the board
level schematic capturing of the design. The board level design
included an IBM 405GP PowerPC for control & management, and a
Xilinx CPLD for reset circuitry and peripheral configuration.
- Designed and completed a
network timing synchronization module for the Schedule Switch Router
system. The redundant clock distribution modules takes in clocks from
various reference sources (BITS, GPS, & SONET) and then generates
and distributes both the system clocks to all other modules and a
periodic heartbeat signal that is used to synchronize all of the
Cetacean routers in the network to be precisely aligned in the time
domain which makes scheduled IP possible. Used a Xilinx Spartan 2 FPGA
for timing control.
3/2000 - 10/2001 SYCAMORE NETWORKS Chelmsford, MA 01824
Senior Hardware Engineer
Designed system boards for the fiber optical networking
Ultra Long Haul Transport System:
- Designed an Optical Gain
Equalization module. This line card provided gain shape reforming of
optical signals in the C or L band to avoid dominance of the power of
one channel over the other DWDM optical signals. Used an MPC8260
processor and Xilinx Spartan FPGA for control of serial EPROM,
Temperature sensors, status & control registers, and Fast Ethernet
transceiver.
- Designed an Interface
Management card for a wavelength interface and switching node. This
line card provided all the BITS and SONET reference timing, control,
and communication of all the other line cards in a system chassis.
Used an MPC8260 processor for control of serial EPROM, Temperature
sensors, status & control registers, Fast Ethernet transceivers, 8
port switch, and 32 port hub. Also used a Xilinx Virtex FPGA for
timing and control circuitry.
7/1998 - 3/2000 INTEL NETWORK SYSTEMS Bedford, MA 01730
Hardware Engineer
Architecturally assisted in the system design of a
Multiservice Concentrator that allowed multiple WAN technologies (T1/E1,
ISDN, xDSL) to be aggregated to LAN technologies, while supporting major
application (VPN, Firewall, QoS) protocols, and traffic types that traverse
the network edge between the LAN and the WAN.
- Designed a 4-port T1/E1 line
card for the Multiservice Concentrator system, which used an open
standard architecture, SA-110 strongARM processor, and 3U Compact PCI
for the LAN/WAN line cards.
- Designed an 8-port 56K
analog Remote Access line card with 10/100BaseT LAN connection, which
used an Altera MAX7000 for control and status registers.
12/1997 - 7/1998 VIDEO NETWORK COMMUNICATIONS Portsmouth,NH
03801
Hardware Engineer
- Designed a 5-port TV/FM
Tuner card, where PC users can access the stations that are overlaid
onto their monitor by dialing into the proprietary video networking
Broadband Switch Hub. The design included Closed Captioning &
other VBI functions to be displayed. Used an MC68360 processor for
data processing, as well as a Lattice ispLSI2000 CPLD for peripheral
handshaking, status registers, reset circuitry, and LED control.
6/1995 - 12/1997 ENTERASYS NETWORKS Rochester, NH 03867
Hardware Engineer
- Designed a 2-port Fast
Ethernet interface module to enhance the functionality of the
SmartSwitch 2000/6000 series.
- Designed Ethernet
repeating/switching modules; redesigned, enhanced, maintained,
supported, and performed cost reductions of existing Ethernet product
lines. Supported customer service & manufacturing through design
and trouble-shooting.
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