------------------------------------------------

Synopsis

Worked as a hardware digital design engineer for over 9 years. Experienced in all phases of new product development from the conceptual stages to high volume production release. Proficient in designing complex FPGAs using Verilog/VHDL, as well as high-speed design methodology and signal integrity, logic & timing simulation, directing PCB layout, hardware debug, design verification & testing, and documentation for production. Creative and methodical approach to a problem solving. Proven track record in leading design teams.

Back to Top

------------------------------------------------

Selected Strengths

• Hardware platforms: PowerPC, 80x86, I960, StrongARM, FPGA, PLD, PCI.
  
• Hardware languages: Verilog and VHDL.
  
• Hardware tools: Viewlogic/Innoveda, OrCAD, Mentor Graphics, Synplicity, Verilog-XL, VCS HDL Simulator, ModelSim, Xilinx ISE, Altera MAX+II, & Timing Designer.
  
• Electrical: Transmission Line Theory & Termination, EMI Suppression, Safety Compliance, Functional & Timing Simulation.
  
• Communication Technologies: SONET, Ethernet, T1/E1, DS3, xDSL, Token Ring, FDDI.
  
• Effective written and verbal abilities.
  
• Strong organizational and interpersonal skills.
  

Back to Top

------------------------------------------------

Education

• UNIVERSITY OF MAINE, Orono, ME. BSEE Technology, 5/1995.
  
• PLYMOUTH STATE COLLEGE, Plymouth, NH. MBA, 2/2000.
  

Back to Top

------------------------------------------------

Experience

11/2001 - 5/2002 CETACEAN NETWORKS Portsmouth, NH 03801

Hardware Engineer

Designed system boards for the Schedule Switch Router enabling Real-Time IP for Internet communication systems:

• Designed a 4 port DS3 interface card for the Schedule Switch Router. Completed the board level schematic capturing of the design. The board level design included an IBM 405GP PowerPC for control & management, and a Xilinx CPLD for reset circuitry and peripheral configuration.
  
• Designed and completed a network timing synchronization module for the Schedule Switch Router system. The redundant clock distribution modules takes in clocks from various reference sources (BITS, GPS, & SONET) and then generates and distributes both the system clocks to all other modules and a periodic heartbeat signal that is used to synchronize all of the Cetacean routers in the network to be precisely aligned in the time domain which makes scheduled IP possible. Used a Xilinx SpartanII FPGA for timing control.
  

3/2000 - 10/2001 SYCAMORE NETWORKS Chelmsford, MA 01824

Hardware Engineer

Designed system boards for the fiber optical networking Ultra Long Haul Transport System:

• Designed an Optical Gain Equalization module. This line card provided gain shape reforming of optical signals in the C or L band to avoid dominance of the power of one channel over the other DWDM optical signals. Used an MPC8260 processor and Xilinx Spartan II FPGA for control of serial EPROM, Temperature sensors, status & control registers, and Fast Ethernet transceiver.
  
• Designed an Interface Management card for a wavelength interface and switching node. This line card provided all the BITS and SONET reference timing, control, and communication of all the other line cards in a system chassis. Used an MPC8260 processor for control of serial EPROM, Temperature sensors, status & control registers, Fast Ethernet transceivers, 8 port switch, and 32 port hub. Also used a Xilinx Virtex FPGA for timing and control circuitry.
  
  

7/1998 - 3/2000 INTEL NETWORK SYSTEMS Bedford, MA 01730

Hardware Engineer

Architecturally assisted in the system design of a Multiservice Concentrator that allowed multiple WAN technologies (T1/E1, ISDN, xDSL) to be aggregated to LAN technologies, while supporting major application (VPN, Firewall, QoS) protocols, and traffic types that traverse the network edge between the LAN and the WAN.

• Designed a 4-port T1/E1 line card for the Multiservice Concentrator system, which used an open standard architecture, SA-110 strongARM processor, and 3U Compact PCI for the LAN/WAN line cards.
  
• Designed an 8-port 56K analog Remote Access line card with 10/100BaseT LAN connection, which used an Altera MAX7000 for control and status registers.
  
  

12/1997 - 7/1998 VIDEO NETWORK COMMUNICATIONS Portsmouth,NH 03801

Hardware Engineer

• Designed a 5-port TV/FM Tuner card, where PC users can access the stations that are overlaid onto their monitor by dialing into the proprietary video networking Broadband Switch Hub. The design included Closed Captioning & other VBI functions to be displayed. Used an MC68360 processor for data processing, as well as a Lattice ispLSI2000 CPLD for peripheral handshaking, status registers, reset circuitry, and LED control.
  
  

6/1995 - 12/1997 ENTERASYS NETWORKS Rochester, NH 03867

Hardware Engineer

• Designed a 2-port Fast Ethernet interface module to enhance the functionality of the SmartSwitch 2000/6000 series.
  
• Designed Ethernet repeating/switching modules; redesigned, enhanced, maintained, supported, and performed cost reductions of existing Ethernet product lines. Supported customer service & manufacturing through design and trouble-shooting.
  

Back to Top

------------------------------------------------