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Still working for Sun from the basement of the house, except when he's sitting by the chiminea or the pool. He has been spotted performing other jobs, though...

Dave's Sun blog

Papers

Talks

"What Really Makes Transactions Faster?", presented at Transact/06, Ottawa, Canada, June 11, 2006.

Patents

Multi-threaded garbage collector employing cascaded memory arrays of task identifiers to implement work stealing queues for task identification and processing (US Patent No. 7,016,923)
Methods and apparatus for controlling speculative execution of instructions based on a multiaccess memory condition (US Patent No. 6,877,088)
Methods and apparatus for performing a memory management technique (US Patent No. 6,862,674)
Speculative exeuction control with programmable indicator and deactivation of multiaccess recovery mechanism (US Patent No. 6,854,048)
Methods and apparatus for executing code while avoiding interference (US Patent No. 6,799,236)
Relaxed lock protocol (US Patent No. 6,735,760)
Mutual exclusion system and method for restarting critical sections of code when preempted during a critical section (US Patent No. 6,697,834)
System and method providing an arrangment for efficiently emulating an operating system call (US Patent No. 6,530,017)
System and method for automatically and selectively promoting object variables to method fields and variables in a digital computer system (US Patent No. 6,308,315)
System and method for efficiently implementing an authenticated communications channel that facilitates tamper detection (US Patent No. 6,289,451)
System and method for synchronizing access to shared variables in a virtual machine in a digital computer system (US Patent No. 6,141,794)
System and method for processing load instruction in accordance with "no-fault" processing facility including arrangement for preserving access fault indicia (US Patent No. 5,903,739. See also US Patent No. 5,712,997).
Emulating a delayed execution on a digital computer having a corresponding precise exception mechanism (US Patent No. 5,778,211)
System and method for emulating a segmented virtual address space by a microprocessor that provides a non-segmented virtual address space (US Patent No. 5,765,206)

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