'Silvius' Test Card Helps Intel
Assess PCI Express Capabilities
Posted September 24, 2002; WW39
From Enterprise Platforms Group
 


The Silvius head-to-head testing configuration

PCI Express* is a high-speed input/output (I/O) technology that is both an Intel initiative and an industry standard that will replace AGP, PCI, and PCI-X.

The PCI Express architecture is designed as a highly flexible, reliable, serial I/O architecture that will scale to the theoretical limits of copper.

PCI Express will comprehend the needs of multiple market segments—desktop, mobile, server, communications, and embedded applications—making it critical to Intel's future. As such, it is vitally important that Intel exhibits leadership and success with it.

Until now, PCI Express has been a conceptual spec on paper. But, in a collaboration between the Enterprise Platforms Goup (EPG) and Desktop Platforms Group (DPG), Intel reached its first major milestone Sept. 1: A field programmable gate array (FPGA)-based version (code-named "Silvius") of a PCI Express design has performed Intel's first communication transaction on hardware.

Silvius is a test card containing an FPGA version of a PCI Express test chip, dubbed "Arden," that will be used to test Intel's PCI Express chipsets. Silvius was created to augment the Arden ASIC (Application Specific Integrated Circuit) pre-silicon validation and give the test software developers an early start.

The Teams Involved
PCI Express is another example of the strong collaboration between the Enterprise Platforms Group (EPG) and Desktop Platforms Group (DPG). The Arden ASIC design team includes approximately 25 engineers across four sites from these groups:

DPG
Folsom Component Validation (FCV) Hardware Tools team (a part of Backend Development [BD])
FCV Software Tools team
Chipset & Software Engineering

EPG
Advanced Platform Development (APD) (a part of the Platform Enabling Division (PED) of the Platform and Products Group [PPG])
Advanced Components Division (ACD) pre-silicon validation team (also part of PPG)

"The benefit of the FPGA-based design is that we can provide better validation of the silicon design, reducing the bugs in Arden and improving the time to market of PCI Express and our chipsets," says Anthony Zilka, APD manager.

"This is an excellent testimony to Operational Excellence—two divisions pooling resources to develop a common solution to meet both groups' [DPG and EPG] needs without duplicating efforts," says Murali Talwai, DPG Validation manager.

Since no other PCI Express hardware exists yet, testing is being done between two Silvius cards in a head-to-head configuration.

"The fact that we have two pieces of hardware that can talk to each other is significant," Anthony adds.

What's Ahead
Intel expects to finalize fixed-silicon Arden ASIC and begin validating Intel's very first PCI Express chipsets in the first half of 2003.